Modern integrated circuits are made up of literally millions of active devices, such as transistors, capacitors, and the like. These devices are initially isolated from each other, but are later interconnected together to form functional circuits. Typical interconnect structures include lateral interconnections, such as metal lines (wirings), and vertical interconnections, such as vias and contacts. Interconnections are increasingly determining the limits of performance and the density of modern integrated circuits. On top of the interconnect structures, bond pads are formed and exposed on the surface of the respective semiconductor “chip.” Electrical connections are made through bond pads to connect the chip to a package substrate or another die.
These semiconductor chips may be used in a wide range of applications such as personal computers, cellular telephones, and gaming devices, among many others. Each chip is actually a small piece of semiconductor material onto and into which has been fabricated a large number of integrated circuits. A semiconductor material is a material that when properly prepared is capable of conducting electricity under certain controllable conditions, such as the application of a small electrical charge. Each of the small components in an integrated circuit is fabricated using successive layers of semiconductor, insulating, and conducting materials arranged in a certain fashion.
The fabrication process begins with providing a substrate of semiconductor material, typically formed in a flat, circular shape called a wafer. Each wafer is cut from an ingot of, for example, silicon, and will be used for the fabrication of a number of semiconductor chips. FIG. 1 is a plan (top) view of a wafer 10. As can be seen in FIG. 1, much of the surface 11 of wafer 10 is subdivided into a number of small square or rectangular areas that are at this stage referred to collectively as dice 12. These dice 12 are separated from each other by linear regions formed on surface 11 and sometimes referred to as scribe lines. For purposes of illustration, dice 16 through 19 are enumerated in FIG. 1 and shown as separated from each other by horizontal scribe line 14 and vertical scribe line 15. Note that the selection of these particular features for illustration is arbitrary, and in the example of FIG. 1 the dice and the scribe lines are substantially identical with respect to each other. Eventually, each good die will become a separate semiconductor chip when the fabrication process is complete.
A number of steps are involved in fabricating the individual structures used to create the electronic components that will form integrated circuits. These will not be described in detail here, although in general they involve the deposition of various layers of material that may selectively be removed, for example by chemical etching, to create the necessary structures. When fabrication is complete, or nearly so, the individual dice may be separated using one of several methods that are sometimes referred to as singulation, or dicing. Singulation is effected by cutting or breaking the wafer apart including, for example, at the pre-formed scribe lines 14 and 15 that are visible in FIG. 1.
It is well known to use a seal ring (which may also be referred to as a die seal, an edge seal, or a scribe seal) to protect a die against potential damage caused by stress induced defects such as crack formation and delamination formed during singulation processes such as sawing, wirebonding or other assembly processes, soldering, or during rigorous environmental testing. The seal ring also provides a protection against moisture penetration. The scribe seal, which is typically formed around a perimeter of the die, is disposed between an active area of the die and a scribe line. It is also well known that stress induced defects such as cracks and delamination are likely to occur near die corners where susceptibility to die failure from such defects is highest. Conventional techniques to reduce damage caused by stress include providing a die layout having a sloped or chamfered corner area rather than a die layout having a sharp corner, e.g., a 90 degree corner, and providing redundant seal rings for added protection. The presence of chamfered corners results in triangular areas, at each corner, within the redundant seal rings. In advanced technology nodes, such as the 40 nm technology node and smaller, these triangular areas are typically left empty, i.e., with no circuitry or other structures disposed therein/thereon. However, at smaller technology nodes, where chip space is at a premium, the presence of any void space on the chip that serves no useful purposes is undesirable.
In another well-known aspect of semiconductor fabrication, due to the large number of processing steps and wide range of processing variables encountered during the fabrication of a conventional device, it has become a practical necessity to incorporate a variety of electronic test structures (“e-test”) on the wafer, to facilitate both the monitoring of the process and the testing of completed wafers. In one conventional configuration, the e-test structures are formed in what are termed “knockout areas,” i.e., areas which would otherwise be devices. In another conventional configuration, the e-test structures are formed in active areas of the chip. As device structures become more complicated, it becomes necessary to incorporate a greater number of test structures, either in the knockout area or in the chip active area. However, as the number of test structures is increased, the constraint imposed by the area of the knockout, or the reduction in available active area, becomes a significant limitation.
Accordingly, it is desirable to provide improved semiconductor chip design. Particularly, it is desirable to provide semiconductor chip designs that reduce the use of void areas, such as those in the seal ring chamfer triangular areas at the chip corners. Still further, it would be desirable to reduce the need for including e-test structures in either the wafer knockout areas or in the chip active areas. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.